Electronic devices and systems such as microprocessors rely on clock signals to provide timing control. Such clock signals typically are based on a precision reference source such as a crystal oscillator. However, a crystal oscillator has a high Q value which results in the spectral energy of the clock signal being concentrated in a very narrow frequency band. The concentration of the energy at the clock frequency as well as its harmonics can lead to emission of electromagnetic interference (EMI) in excess of that permitted under applicable government regulations.
In certain electronic systems it is possible to dither or modulate the frequency of the clock signal in order to spread its spectral energy over a band of frequencies. The result of this spreading is a reduction of the energy of the clock or harmonics of the clock that might otherwise appear at any particular frequency or band. Such dithering of the clock signal facilitates compliance with the applicable government regulations.
Various approaches have been proposed for dithering a clock signal. For example, Hewlett-Packard has developed a technique for dithering the reference divider of a phase-locked loop (PLL) between values to create a modulation profile. U.S. Pat. No. 5,610,955 is directed to a variation of such technique that dithers both the reference divider and the feedback divider in a PLL in order to spread the resultant clock signal.
Although these approaches are successful in dithering the clock signal, there are however a number of disadvantages. For example, by dithering the feedback divider and/or reference divider the PLL is continually being driven out of lock. This means that the PLL loop dynamics (e.g., unity-gain frequency, damping, etc.) affect the performance of the resulting modulation. If the loop bandwidth is too narrow, the modulating profile is filtered. If the loop bandwidth is set up to be very wide, compromises must be made regarding the precision of the resulting output frequency and step size. As is known, wide loop bandwidths require small integers in the feedback divider path.
Another disadvantage of such conventional approaches is the requirement for significant additional hardware in order to implement clock dithering. For example, additional dividers are oftentimes necessary. Such additional hardware occupies chip area and increases the size and/or cost of the electronic device.
In view of the aforementioned shortcomings associated with conventional approaches, there is a strong need in the art for an improved method and circuit for dithering a clock signal. In particular, there is a strong need for a method and circuit for dithering a clock signal generated by a PLL which avoids continually driving the PLL out of lock. Moreover, there is a strong need in the art for a circuit and method for dithering a clock signal generated by a PLL which does not require significant additional hardware.